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cy2077 high-accuracy eprom programmable single-pll clock generator cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-07210 rev. *e revised april 07, 2010 features high-accuracy pll with 12-bit multiplier and 10-bit divider eprom programmability 3.3v or 5v operation operating frequency ? 390 khz?133 mhz at 5v ? 390 khz?100 mhz at 3.3v reference input from either a 10?30 mhz fundamental toned crystal or a 1?75 mhz external clock eprom selectable ttl or cmos duty cycle levels sixteen selectable post-divide options, using either pll or reference oscillator/external clock programmable pwr_dwn or oe pin, with asynchronous or synchronous modes low jitter outputs typically ? 80 ps at 3.3v/5v controlled rise and fall times and output slew rate available in both commercial a nd industrial temperature ranges factory programmable device options benefits enables synthesis of highly accurate and stable output clock frequencies with zero ppm enables quick turnaround of custom frequencies supports industry standard design platforms services most pc, networking, and consumer applications lowers cost of oscillator as pll can be programmed to a high frequency using either a low-fr equency, low-cost crystal, or an existing system clock duty cycle centered at 1.5v or v dd /2 provides flexibility to service most ttl or cmos applications provides flexibility in output configurations and testing enables low-power operation or output enable function and flexibility for system applications, through selectable instanta- neous or synchronous change in outputs suitable for most pc, consumer, and networking applications has lower emi than oscillators suitable to fit most applications easy customization and fast turnaround oscillator xtalin pwr_dwn configuration crystal clkout / 1, 2, 4, 8, 16, 32, 64, 128 or oe mux high accuracy pll eprom q 10 bits p 12 bits phase detector charge pump vco or external clock note 1. when using an external clock source, leave xtalout floating. xtalout [1] logic block diagram [+] feedback
cy2077 document number: 38-07210 rev. *e page 2 of 14 pinouts figure 1. pin diagram - 8 pin top view functional description cy2077 is an eprom-programmable, high-accuracy, general-purpose, pll-based design for use in applications such as modems, disk drives, cd-rom drives, video cd players, dvd players, games, set-top boxes, and data/telecommunications. cy2077 can generate a clock output up to 133 mhz at 5v or 100 mhz at 3.3v. it has been designed to give the customer a very accurate and stable cl ock frequency wi th little to zero ppm error. cy2077 contains a 12-bit feedback counter divider and 10-bit reference counter divider to obtain a very high resolution to meet the needs of stringent design sp ecifications. furthermore, there are eight output divide options of /1, /2, /4, /8, /16, /32, /64, and /128. the output divider can se lect between the pll and crystal oscillator output/external clock, providing a total of 16 different options to add more flexibility in designs. ttl or cmos duty cycles can be selected. power management with the cy2077 is also very flexible. the user can choose either a pwr_dwn, or an oe feature with which both have integrated pull up resistors. pwr_dwn and oe signals can be programmed to have asynchronous and synchronous timing with respect to the output signal. there is a weak pull down on the output that pulls clkout low when either the pwr_dwn or oe signal is low. this weak pull down can easily be overridden by another clock signal in designs where multiple clock signals share a signal path. multiple options for output selection, better power distribution layout, and controlled rise and fall times enable the cy2077 to be used in applications that require low jitter and accurate reference frequencies. eprom configuration block table 2. eprom adjustable features pll output frequency cy2077 contains a high-resolution pll with 12-bit multiplier and 10-bit divider. [2] the output frequency of the pll is determined by the following formula: where p is the feedback counter value and q is the reference counter value. p and q are eprom programmable values. the calculation of p and q values for a given pll output frequency is handled by the cyberclocks ? software. refer to ? ?programming procedures? on page 12? for details. 1 2 3 4 5 8 7 6 v dd xtalout xtalin pd/oe v ss clkout v ss v ss table 1. pin definition - 8 pin pin name pin # pin description v dd 1 voltage supply v ss 5,6,7 ground (all the pins must be grounded) x d 2 crystal output (leave this pin floating when external reference is used) x g 3 crystal input or external input reference pwr_dwn / oe 4 eprom programmable power down or output enable pin. pwr_dwn is active low. oe is active high. weak pull up. clkout 8 clock output. weak pull down eprom adjustable features adjust freq. feedback counter value (p) reference counter value (q) output divider selection duty cycle levels (ttl or cmos) power management mode (oe or pwr_dwn) power management timing (synch ronous or asynchronous) f pll 2p5 + ?? ? q2 + ?? --------------------------- f ref ? = note 2. when using cyclocks, note that the pll frequency range is from 50 mhz to 250 mhz for 5v v dd supply, and 50 mhz to 180 mhz for 3v v dd supply. the output frequency is determined by the selected output divider. [+] feedback
cy2077 document number: 38-07210 rev. *e page 3 of 14 power management features pwr_dwn and oe options are configurable by eprom programming for the cy2077. in pwr_dwn mode, all active circuits are powered down when the control pin is set low. when the control pin is set back high, both the pll and oscillator circuit must relock. in the case of oe, the output is three-stated and weakly pulled down when the control pin is set low. the oscillator and pll are still active in this state, which leads to a quick clock output return when the control pin is set back high. additionally, pwr_dwn and oe can be configured to occur asynchronously or synchronously with respect to clkout. in asynchronous mode, pwr_dwn or oe disables clkout immediately (allowing for logic delays), without respect to the current state of clkout. synchronous mode prevents output glitches by waiting for the next falling edge of clkout after pwr_dwn, or oe becomes asse rted. in either asynchronous or synchronous setting, the output is always enabled synchronously by waiting for the next falling edge of clkout. absolute maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. supply voltage .................................................. ?0.5 to +7.0v input voltage ........................................... ?0.5v to v dd +0.5v storage temperature (non-condensing)...... ?55c to +150c junction temperature.................................................. 150c static discharge voltage........................................... > 2000v (per mil-std-883, method 3015) operating conditions for co mmercial temperature device table 3. device functionality: output frequencies symbol description condition min max unit fo output frequency v dd = 4.5?5.5v 0.39 133 mhz v dd = 3.0?3.6v 0.39 100 mhz parameter description min max unit v dd supply voltage 3.0 5.5 v t a operating temperat ure, ambient 0 +70 c c ttl max. capacitive load on outputs for ttl levels v dd = 4.5 ? 5.5v, output frequency = 1 ? 40 mhz v dd = 4.5 ? 5.5v, output frequency = 40 ? 125 mhz v dd = 4.5 ? 5.5v, output frequency = 125 ? 133 mhz 50 25 15 pf pf pf c cmos max. capacitive load on outputs for cmos levels v dd = 4.5 ? 5.5v, output frequency = 1 ? 40 mhz v dd = 4.5 ? 5.5v, output frequency = 40 ? 125 mhz v dd = 4.5 ? 5.5v, output frequency = 125 ? 133 mhz v dd = 3.0 ? 3.6v, output frequency = 1 ? 40 mhz v dd = 3.0 ? 3.6v, output frequency = 40 ? 100 mhz 50 25 15 30 15 pf pf pf pf pf x ref reference frequency, input crystal with c load = 10 pf 10 30 mhz reference frequency, external clock source 1 75 mhz t pu power up time for all vdd's to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms [+] feedback
cy2077 document number: 38-07210 rev. *e page 4 of 14 electrical characteristics t a = 0 c to +70 c parameter description test conditions min typ max unit v il low-level input voltage v dd = 4.5 ? 5.5v v dd = 3.0 ? 3.6v 0.8 0.2v dd v v v ih high-level input voltage v dd = 4.5 ? 5.5v v dd = 3.0 ? 3.6v 2.0 0.7v dd v v v ol low-level output voltage v dd = 4.5 ? 5.5v, i ol = 16 ma v dd = 3.0 ? 3.6v, i ol = 8 ma 0.4 0.4 v v v ohcmos high-level output voltage cmos levels v dd = 4.5 ? 5.5v, i oh = ?16 ma v dd = 3.0 ? 3.6v, i oh = ?8 ma v dd ? 0.4 v dd ? 0.4 v v v ohttl high-level output voltage ttl levels v dd = 4.5 ? 5.5v, i oh = ?8 ma 2.4 v i il input low current v in = 0v 10 ? a i ih input high current v in = v dd 5 ? a i dd power supply current unloaded v dd = 4.5 ? 5.5v, output frequency <= 133 mhz v dd = 3.0 ? 3.6v, output frequency <= 100 mhz 45 25 ma ma i dds [3] stand-by current (pd = 0) v dd = 4.5 ? 5.5v v dd = 3.0 ? 3.6v 25 10 100 50 ? a r up input pull up resistor v dd = 4.5 ? 5.5v, v in = 0v v dd = 4.5 ? 5.5v, v in = 0.7v dd 1.1 50 3.0 100 8.0 200 m ? k ? i oe_clkout clkout pull down current v dd = 5.0 20 ? a note 3. if external reference is used, it is required to st op the reference (set reference to low) during power down. [+] feedback
cy2077 document number: 38-07210 rev. *e page 5 of 14 output clock switching ch aracteristics commercial over the operating range [4] parameter description test conditions min typ max unit t 1w output duty cycle at 1.4v, v dd = 4.5 ? 5.5v t 1w = t 1a ? t 1b 1 ? 40 mhz, c l <= 50 pf 40 ? 125 mhz, c l <= 25 pf 125 ? 133 mhz, c l <= 15 pf 45 45 45 55 55 55 % % % t 1x output duty cycle at v dd /2, v dd = 4.5 ? 5.5v t 1x = t 1a ? t 1b 1 ? 40 mhz, c l <= 50 pf 40 ? 125 mhz, c l <= 25 pf 125 ? 133 mhz, c l <= 15 pf 45 45 45 55 55 55 % % % t 1y output duty cycle at v dd /2, v dd = 3.0 ? 3.6v t 1y = t 1a ? t 1b 1 ? 40 mhz, c l <= 30 pf 40 ? 100 mhz, c l <= 15 pf 45 40 55 60 % % t 2 output clock rise time between 0.8 ? 2.0v, v dd = 4.5v ? 5.5v, c l = 50 pf between 0.8 ? 2.0v, v dd = 4.5v ? 5.5v, c l = 25 pf between 0.8 ? 2.0v, v dd = 4.5v ? 5.5v, c l = 15 pf between 0.2v dd ? 0.8v dd , v dd = 4.5v ? 5.5v, c l = 50 pf between 0.2v dd ? 0.8v dd , v dd = 3.0v ? 3.6v, c l = 30 pf between 0.2v dd ? 0.8v dd , v dd = 3.0v ? 3.6v, c l = 15 pf 1.8 1.2 0.9 3.4 4.0 2.4 ns ns ns ns ns ns t 3 output clock fall time between 0.8v ?2.0v, v dd = 4.5v ? 5.5v, c l = 50 pf between 0.8 ? 2.0v, v dd = 4.5v ? 5.5v, c l = 25 pf between 0.8 ? 2.0v, v dd = 4.5v ? 5.5v, c l = 15 pf between 0.2v dd ? 0.8v dd , v dd = 4.5v ? 5.5v, c l = 50 pf between 0.2v dd ? 0.8v dd , v dd = 3.0v ? 3.6v, c l = 30 pf between 0.2v dd ? 0.8v dd , v dd = 3.0v ? 3.6v, c l = 15 pf 1.8 1.2 0.9 3.4 4.0 2.4 ns ns ns ns ns ns t 4 startup time out of power down pwr_dwn pin low to high [5] 12ms t 5a power down delay time (synchronous setting) pwr_dwn pin low to output low (t= period of output clk) t/2 t + 10 ns t 5b power down delay time (asynchronous setting) pwr_dwn pin low to output low 10 15 ns t 6 power up time from power on [5] 12ms t 7a output disable time (synchronous setting) oe pin low to output high-z (t= period of output clk) t/2 t + 10 ns t 7b output disable time (asynchronous setting) oe pin low to output high-z 10 15 ns t 8 output enable time (always synchronous enable) oe pin low to high (t= period of output clk) t1.5t + 25n s ns t 9 peak-to-peak period jitter v dd = 3.0v ? 3.6v, 4.5v ? 5.5v, fo > 33 mhz, v co > 100 mhz v dd = 3.0v ? 5.5v, fo < 33 mhz 80 0.3% 150 1% ps % of f o notes 4. not all parameters measured in production testing. 5. oscillator start time can not be guaranteed for all crystal types . this specification is for operation with at cut crystals w ith esr < 70 ??? [+] feedback
cy2077 document number: 38-07210 rev. *e page 6 of 14 operating conditions for i ndustrial temper ature device electrical characteristics t a = ?40 c to +85 c parameter description min max unit v dd supply voltage 3.0 5.5 v t a operating temperatur e, ambient ?40 +85 c c ttl max. capacitive load on outputs for ttl levels v dd = 4.5 ? 5.5v, output frequency = 1 ? 40 mhz v dd = 4.5 ? 5.5v, output frequency = 40 ? 125 mhz v dd = 4.5 ? 5.5v, output frequency = 125 ? 133 mhz 35 15 10 pf pf pf c cmos max. capacitive load on outputs for cmos levels v dd = 4.5 ? 5.5v, output frequency = 1 ? 40 mhz v dd = 4.5 ? 5.5v, output frequency = 40 ? 125 mhz v dd = 4.5 ? 5.5v, output frequency = 125 ? 133 mhz v dd = 3.0 ? 3.6v, output frequency = 1 ? 40 mhz v dd = 3.0 ? 3.6v, output frequency = 40 ? 100 mhz 35 15 10 20 10 pf pf pf pf pf x ref reference frequency, input crystal with c load = 10 pf 10 30 mhz reference frequency, external clock source 1 75 mhz t pu power up time for all vdd's to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms parameter description test conditions min typ. max unit v il low-level input voltage v dd = 4.5 ? 5.5v v dd = 3.0 ? 3.6v 0.8 0.2v dd v v v ih high-level input voltage v dd = 4.5 ? 5.5v v dd = 3.0 ? 3.6v 2.0 0.7v dd v v v ol low-level output voltage v dd = 4.5 ? 5.5v, i ol = 16 ma v dd = 3.0 ? 3.6v, i ol = 8 ma 0.4 0.4 v v v ohcmos high-level output voltage, cmos levels v dd = 4.5 ? 5.5v, i oh = ?16 ma v dd = 3.0 ? 3.6v, i oh = ?8 ma v dd ? 0.4 v dd ? 0.4 v v v ohttl high-level output voltage, ttl levels v dd = 4.5 ? 5.5v, i oh = ?8 ma 2.4 v i il input low current v in = 0v 10 ? a i ih input high current v in = v dd 5 ? a i dd power supply current, unloaded v dd = 4.5 ? 5.5v, output frequency <= 133 mhz v dd = 3.0 ? 3.6v, output frequency <= 100 mhz 45 25 ma ma i dds [3] stand-by current (pd = 0) v dd = 4.5 ? 5.5v v dd = 3.0 ? 3.6v 25 10 100 50 ? a r up input pull up resistor v dd = 4.5 ? 5.5v, v in = 0v v dd = 4.5 ? 5.5v, v in = 0.7v dd 1.1 50 3.0 100 8.0 200 m ? k ? i oe_clkout clkout pull down current v dd = 5.0 20 ? a [+] feedback
cy2077 document number: 38-07210 rev. *e page 7 of 14 output clock switching ch aracteristics industrial over the operating range [4] parameter description test conditions min typ. max unit t 1w output duty cycle at 1.4v, v dd = 4.5 ? 5.5v t 1w = t 1a ? t 1b 1 ? 40 mhz, c l <= 35 pf 40 ? 125 mhz, c l <= 15 pf 125 ? 133 mhz, c l <= 10 pf 45 45 45 55 55 55 % % % t 1x output duty cycle at v dd /2, v dd = 4.5 ? 5.5v t 1x = t 1a ? t 1b 1 ? 40 mhz, c l <= 35 pf 40 ? 125 mhz, c l <= 15 pf 125 ? 133 mhz, c l <= 10 pf 45 45 45 55 55 55 % % % t 1y output duty cycle at v dd /2, v dd = 3.0 ? 3.6v t 1y = t 1a ? t 1b 1? 40 mhz, c l <= 20 pf 40 ? 100 mhz, c l <= 10 pf 45 40 55 60 % % t 2 output clock rise time between 0.8 ? 2.0v, v dd = 4.5v ? 5.5v, c l = 35 pf between 0.8 ? 2.0v, v dd = 4.5v ? 5.5v, c l = 15 pf between 0.8 ? 2.0v, v dd = 4.5v ? 5.5v, c l = 10 pf between 0.2v dd ? 0.8v dd , v dd = 4.5v ? 5.5v, c l = 35 pf between 0.2v dd ? 0.8v dd , v dd = 3.0v ? 3.6v, c l = 20 pf between 0.2v dd ? 0.8v dd , v dd = 3.0v ? 3.6v, c l = 10 pf 1.8 1.2 0.9 3.4 4.0 2.4 ns ns ns ns ns ns t 3 output clock fall time between 0.8v ? 2.0v, v dd = 4.5v ? 5.5v, c l = 35 pf between 0.8 ? 2.0v, v dd = 4.5v ? 5.5v, c l = 15 pf between 0.8 ? 2.0v, v dd = 4.5v ? 5.5v, c l = 10 pf between 0.2v dd ? 0.8v dd , v dd = 4.5v ? 5.5v, c l = 35 pf between 0.2v dd ? 0.8v dd , v dd = 3.0v ? 3.6v, c l = 20 pf between 0.2v dd ? 0.8v dd , v dd = 3.0v ? 3.6v, c l = 10 pf 1.8 1.2 0.9 3.4 4.0 2.4 ns ns ns ns ns ns t 4 startup time out of power down pwr_dwn pin low to high [5] 12ms t 5a power down delay time (synchronous setting) pwr_dwn pin low to output low (t= period of output clk) t/2 t+10 ns t 5b power down delay time (asynchronous setting) pwr_dwn pin low to output low 10 15 ns t 6 power up time from power on [5] 12ms t 7a output disable time (synchronous setting) oe pin low to output high-z (t= period of output clk) t/2 t + 10 ns t 7b output disable time (asynchronous setting) oe pin low to output high-z 10 15 ns t 8 output enable time (always synchronous enable) oe pin low to high (t = period of output clk) t1.5t + 25ns ns t 9 peak-to-peak period jitter v dd = 3.0v ? 3.6v, 4.5v ? 5.5v, fo > 33 mhz, v co > 100 mhz v dd = 3.0v ? 5.5v, fo < 33 mhz 80 0.3% 150 1% ps % of f o [+] feedback
cy2077 document number: 38-07210 rev. *e page 8 of 14 switching waveforms figure 2. duty cycle timing (t 1w , t 1x , t 1y ) figure 3. output rise/fall time figure 4. power down timing (synchronous and asynchronous modes) figure 5. power up timing figure 6. output enable timing (synchronous and asynchronous modes) notes 6. in synchronous mode, the power down or output three-state is not initiated until the next falling edge of the output clock. 7. in asynchronous mode, the power down or output three-state occu rs within 25 ns regardless of position in the output clock cyc le. t 1a t 1b output output t 2 v dd 0v t 3 clkout vdd t4 1/f t5a vil vih power down 0v 1/f t5b clkout t (synchronous [ 6] ) (asynchronous [ 7] ) clkout v dd t6 1/f v dd ? 10% power up 0v min 30 ? s max 30 ms clkout v dd output enable 0v vil t7a t8 high impedance clkout t7b t8 high impedance t (synchronous [ 6] ) (asynchronous [ 7] ) vih [+] feedback
cy2077 document number: 38-07210 rev. *e page 9 of 14 typical rise/fall time [8] trends for cy2077 figure 7. rise/fall time vs. vdd over temperatures figure 8. rise/fall time vs. output loads over temperatures rise time vs. vdd -- cmos duty cycle cload = 15pf 1.00 1.20 1.40 1.60 1.80 2.00 2.7 3.0 3.3 3.6 3.9 vdd (v) rise time (ns) -40c 25c 85c fall time vs. vdd -- cmos duty cycle cload = 15pf 1.00 1.20 1.40 1.60 1.80 2.00 2.7 3.0 3.3 3.6 3.9 vdd (v) fall time (ns) -40c 25c 85c rise time vs. vdd -- ttl duty cycle cload = 15pf 0.20 0.30 0.40 0.50 0.60 0.70 4.0 4.5 5.0 5.5 6.0 vdd (v) rise time (ns) -40c 25c 85c fall time vs. vdd -- ttl duty cycle cload = 15pf 0.20 0.30 0.40 0.50 0.60 0.70 4.0 4.5 5.0 5.5 6.0 vdd (v) fall time (ns) -40c 25c 85c rise time vs. cload over temperature vdd = 3.3v, cmos output 1.00 1.50 2.00 2.50 10 15 20 25 30 35 cload (pf) rise time (ns) -40c 25c 85c fall time vs. cload over temperature vdd = 3.3v, cmos output 1.00 1.50 2.00 10 15 20 25 30 35 cload (pf) fall time (ns) -40c 25c 85c note 8. rise/fall time for cmos output is measured between 1.2 v dd and 0.8 v dd . rise/fall time for ttl output is measured between 0.8v and 2.0v. [+] feedback
cy2077 document number: 38-07210 rev. *e page 10 of 14 typical duty cycle [9] trends for cy2077 figure 9. duty cycle vs. v dd over temperatures figure 10. duty cycle vs. output load figure 11. duty cycle vs. output frequency over temperatures duty cycle vs. vdd over temperature (ttl duty cycle output, fout=50mhz, cload = 50pf) 45.00 47.00 49.00 51.00 53.00 55.00 4.0 4.5 5.0 5.5 6.0 vdd (v) duty cycle (%) -40c 25c 85c duty cycle vs. vdd over temperature (cmos duty cycle ouput, fout=50mhz, cload=50pf) 45.00 47.00 49.00 51.00 53.00 55.00 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 vdd (v) duty cycle (%) -40c 25c 85c duty cycle vs. cload with various vdd (fout = 50mhz, temp = 25c) 45.00 47.00 49.00 51.00 53.00 55.00 10 15 20 25 30 35 40 45 50 55 cload (pf) duty cycle (%) vdd=4.5v vdd=5.0v vdd=5.5v output duty cycle vs. fout over temperature (vdd = 5v, cload = 15pf) 50.00% 51.00% 52.00% 53.00% 54.00% 55.00% 20 30 40 50 60 70 80 output frequency (mhz) output dc (%) 25c 85c -40c note 9. duty cycle is measured at 1.4v for ttl output and 0.5 v dd for cmos output. [+] feedback
cy2077 document number: 38-07210 rev. *e page 11 of 14 typical jitter trends for cy2077 figure 12. period jitter (pk-pk) vs. v dd over temperatures figure 13. period jitter (pk-pk) vs. output frequency over temperatures period jitter (pk-pk) vs. vdd over temperatures (fout=40mhz, cload = 30pf) 0 20 40 60 80 100 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 vdd (v) period jitter (ps) -40c 25c 85c output jitter (pk-pk) vs. output frequency (vdd=3.3v, cload=15pf , cmos output) 0 20 40 60 80 10 0 0 20406080100120140 output frequency (mhz) jitter (ps) 25c -40c 85c output jitter(pk-pk) vs. output frequency (vdd=5.0v, cload=15pf, cmos output) 0 20 40 60 80 10 0 0 20 406080100120140 output frequency (mhz) jitter (ps) 25c -40c 85c [+] feedback
cy2077 document number: 38-07210 rev. *e page 12 of 14 programming procedures currently the cy2077 is available only as a field-programmable device, as indicated by an ?f? in the ordering code. devices may be programmed using the cy3670 programmer, or through programmers available from third party programmer manufacturers such as hi-lo systems and bp micro. programming services are also available from third parties, including some cypress distribution partners. to generate a jedec format programming file, customers must use cyclocks software. this software automatically calculates the output frequencies t hat can be generated by cy2077 devices. the cyclocks software is a subset of the larger software tool cyberclocks, which is available free of charge from the cypress web site ( http://www.cypress.com ). cyberclocks is installed on a pc and must not be confused with the web-based application cy berclocks online. for high volume designs, factory programming of customer-specific configurations is available on other 8-pin devices such as the cy22180, cy22801 and cy22381. factory programming is no longer offered for new designs using the cy2077. ordering information order code [11] package name package type operating temp. range operating voltage pb-free cy2077fsxc s8 8-pin soic commercial (t = 0c to 70c) 3.3v or 5v cy2077fsxct s8 8-pin soic?tape and reel commercial (t = 0c to 70c) 3.3v or 5v cy2077fzz z8 8-pin tssop commercial (t = 0c to 70c) 3.3v or 5v cy2077fzxi z8 8-pin tssop industrial (t = ?40c to 85c) 3.3v or 5v cy2077fzxit z8 8-pin tssop?tape and reel industrial (t = ?40c to 85c) 3.3v or 5v table 4. obsolete or not for new designs original device replacement device order code [10, 11] description order code description cy2077sc-xxx none cy2077sc-xxxt none cy2077si-xxx none cy2077si-xxxt none cy2077sxc-xxx none cy2077sxc-xxxt none CY2077ZC-XXX none CY2077ZC-XXXt none cy2077zi-xxx none cy2077zi-xxxt none cy2077zxc-xxx none cy2077zxc-xxxt none cy2077fsi soic, industrial (t = ?40c to 85c) cy2077fsxc pb-free soic, commercial cy2077fz tssop, commercial (t = 0c to 70c) cy2077fzz pb-free tssop, commercial cy2077fzi tssop, industrial (t = ?40c to 85c) cy2077fzxi pb-free tssop, industrial notes 10. the cy2077sc-xxx(t), cy2077si-xxx(t), cy 2077sxc-xxx(t), CY2077ZC-XXX(t), cy2077zi-xxx (t) andcy2077zxc-xxx(t), are factory pr ogrammed configurations. factory programming is available for high-volume design opportuniti es. for more details, contact your local cypress fae or cypr ess sales representative. 11. the cy2077f are field programmable. for more details, contact your local cypress fae or cypress sales representative. [+] feedback
cy2077 document number: 38-07210 rev. *e page 13 of 14 package diagrams figure 14. 8-pin (150 mil body) soic (small outline ic) figure 15. 8-pin (4.40-mm body) tssop (thin shrunk small outline package) 51-85066 *d 51-85093 *b [+] feedback
document number: 38-07210 rev. *e revised april 07, 2010 page 14 of 14 cyberclocks is a trademark of cypress semiconductor. all product or company names mentioned in this document are the trademarks of their respective holders. all products and company names mentioned in this document may be the trademarks of their respective holders. cy2077 ? cypress semiconductor corporation, 2002-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb document title: cy2077 high-accuracy eprom programmable single-pll clock generator document number: 38-07210 rev. ecn orig. of change sumbission date description of change ** 111727 dsg 02/07/02 convert from spec number: 38-01009 to 38-07210 *a 114938 ckn 07/24/02 added table and notes to page 11 *b 121843 rbi 12/14/02 power up requirements adde d to operating conditions information *c 2104546 pyg/kvm /aesa see ecn updated ordering information table replaced the ?custom configuration request procedure? section with ?programming procedures? updated package diagrams *d 2631183 kvm/aesa 01/06/ 09 updated template. cy2077fs removed from the active part number table. added cy2077fzxi and cy2077fzxit to the ordering information table. corrected wording on p. 2 about when the weak output pull-down is active. added to table 1 to indicate that pwr_dwn is active low and oe is active high. *e 2905892 cxq 04/07/10 removed inactive part cy 2077fs from table 4. updated package diagrams. [+] feedback

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